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50 mhz to 1000 mhz quadrature demodulator ad8348 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features integrated i/q demodulator with if vga amplifier operating if frequency 50 mhz to 1000 mhz (3 db if bw of 500 mhz driven from r s = 200 ) demodulation bandwidth 75 mhz linear-in-decibel agc range 44 db third-order intercept iip3 +28 dbm @ minimum gain (f if = 380 mhz) iip3 ?8 dbm @ maximum gain (f if = 380 mhz) quadrature demodulation accuracy phase accuracy 0.5 amplitude balance 0.25 db noise figure 11 db @ maximum gain (f if = 380 mhz) lo input ?10 dbm single supply 2.7 v to 5.5 v power-down mode compact, 28-lead tssop package applications qam/qpsk demodulator w-cdma/cdma/gsm/nadc wireless local loop lmds functional block diagram divide by 2 phase splitter loin loip 8 imx o vcmo vref vcmo 13 iof s 6 iain 4 iopp 3 iopn 5 vcmo 16 qofs 24 envg 21 qxmo 19 mxin 18 mxip 23 qain 25 qopp 26 qopn 1 28 11 10 gain control 17 bias cell ifip ifin vgin 15 enbl 14 v ref 03678-001 ad8348 figure 1. general description the ad8348 is a broadband quadrature demodulator with an integrated intermediate frequency (if), variable gain amplifier (vga), and integrated baseband amplifiers. it is suitable for use in communications receivers, performing quadrature demodulation from if directly to baseband frequencies. the baseband amplifiers are designed to interface directly with dual-channel adcs, such as the ad9201 , ad9283 , and ad9218 , for digitizing and post- processing. the if input signal is fed into two gilbert cell mixers through an x-amp? vga. the if vga provides 44 db of gain control. a precision gain control circuit sets a linear-in-decibel gain char- acteristic for the vga and provides temperature compensation. the lo quadrature phase splitter employs a divide-by-2 frequency divider to achieve high quadrature accuracy and amplitude balance over the entire operating frequency range. optionally, the if vga can be disabled and bypassed. in this mode, the if signal is applied directly to the quadrature mixer inputs via the mxip and mxin pins. separate i- and q-channel baseband amplifiers follow the baseband outputs of the mixers. the voltage applied to the vcmo pin sets the dc common-mode voltage level at the baseband outputs. typically, vcmo is connected to the internal vref voltage, but it can also be connected to an external voltage. this flexibility allows the user to maximize the input dynamic range to the adc. connecting a bypass capacitor at each offset compensation input (iofs and qofs) nulls dc offsets produced in the mixer. offset compensation can be overridden by applying an external voltage at the offset compensation inputs. the mixers outputs are brought off-chip for optional filtering before final amplification. inserting a channel selection filter before each baseband amplifier increases the baseband amplifiers signal handling range by reducing the amplitude of high level, out-of-channel interferers before the baseband signal is fed into the i/q baseband amplifiers. the single-ended mixer output is amplified and converted to a differential signal for driving adcs.
ad8348 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 equivalent circuits ........................................................................... 9 typical performance characteristics ........................................... 11 vga and demodulator ............................................................. 11 demodulator using mxip and mxin .................................... 14 final baseband amplifiers ........................................................ 15 vga/demodulator and baseband amplifier ......................... 16 theory of operation ...................................................................... 18 vga .............................................................................................. 18 downconversion mixers ........................................................... 18 phase splitter ............................................................................... 18 i/q baseband amplifiers ........................................................... 18 enable........................................................................................... 18 baseband offset cancellation ................................................... 18 applications ..................................................................................... 20 basic connections ...................................................................... 20 power supply ............................................................................... 20 device enable ............................................................................. 20 vga enable ................................................................................ 20 gain control ............................................................................... 20 lo inputs ..................................................................................... 20 if inputs ...................................................................................... 20 mx inputs ................................................................................... 20 baseband outputs ...................................................................... 21 output dc bias level ................................................................ 21 interfacing to detector for agc operation ............................... 21 baseband filters .......................................................................... 22 lo generation ............................................................................ 23 evaluation board ........................................................................ 23 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 4/06rev. 0 to rev. a updated format..................................................................universal changes to specifications ................................................................ 3 changes to if inputs section ........................................................ 20 changes to evaluation board section.......................................... 23 changes to table 6.......................................................................... 27 changes to ordering guide .......................................................... 28 8/03revision 0: initial version
ad8348 rev. a | page 3 of 28 specifications v s = 5 v, t a = 25 o c, f lo = 380 mhz, f if = 381 mhz, p lo = ?10 dbm, r s (lo) = 50 , r s (ifip and mxip/mxin) = 200 , unless otherwise noted. table 1. parameter conditions min typ max unit operating conditions lo frequency range external input = 2 lo frequency 100 2000 mhz if frequency range 50 1000 mhz baseband bandwidth 75 mhz lo input level 50 source ?12 ?10 0 dbm v supply (v s ) 2.7 5.5 v temperature range ?40 +85 c if front end with vga ifip to imxo (qmxo), envg = 5 v, imxo/qmxo load = 1.5 k input impedance measured differentially across mxip/mxin 200||1.1 ||pf gain control range 44 db maximum conversion voltage gain vgin = 0.2 v (maximum voltage gain) 25.5 db minimum conversion voltage gain vgin = 1.2 v (minimum voltage gain) ?18.5 db 3 db bandwidth 500 mhz gain control linearity vgin = 0.4 v (+ 21 db) to 1.1 v (?14 db) 0.5 db if gain flatness f if = 380 mhz 5% (vgin = 1.2 v) 0.1 db p-p f if = 900 mhz 5% (vgin = 1.2 v) 1.3 db p-p input 1 db compression point (p1db) vg in = 0.2 v (maximum gain) ?22 dbm vgin = 1.2 v (maximum gain) +13 dbm second-order input intercept (iip2) if1 = 385 mhz, if2 = 386 mhz +3 dbm each tone from 200 source, 65 dbm vgin = 1.2 v (minimum gain) ?42 dbm each tone from 200 source, 18 dbm vgin = 0.2 v (maximum gain) third-order input intercept (iip3) if1 = 381 mhz, if2 = 381.02 mhz each tone 10 db below p1db from 200 source, 28 dbm vgin = 1.2 v (minimum gain) each tone 10 db below p1db from 200 source, ?8 dbm vgin = 0.2 v (maximum gain) lo leakage measured at ifip, ifin ?80 dbm measured at imxo/qmxo (lo = 50 mhz) ?60 dbm demodulation bandwidth small signal 3 db bandwidth 75 mhz quadrature phase error 1 lo = 380 mhz (loip/loin 760 mhz) ?0.7 0.1 +0.7 degrees vs. temperature ?0.0032 /c vs. baseband frequency (dc to 30 mhz) +0.01 /mhz i/q amplitude imbalance 1 ?0.3 0.05 +0.3 db vs. temperature 0 db/c vs. baseband frequency (dc to 30 mhz) 0.0125 db noise figure (double sideband) maximum gain, from 200 source, f if = 380 mhz 10.75 db mixer output impedance 40 capacitive load shunt from imxo, qmxo to vcmo 0 10 pf resistive load shunt from imxo, qmxo to vcmo 200 1.5 k mixer peak output current 2.5 ma
ad8348 rev. a | page 4 of 28 parameter conditions min typ max unit if front end without vga from mxip, mxin to imxo (qmxo), envg = 0 v, imxo/qmxo load = 1.5 k input impedance measured differentially across mxip/mxin 200||1.5 ||pf conversion voltage gain 10.5 db 3 db output bandwidth 75 mhz if gain flatness f if = 380 mhz 5% 0.1 db p-p f if = 900 mhz 5% 0.15 db p-p input 1 db compression point (p1db) ?4 dbm third-order input intercept (iip3) if1 = 381 mhz, if2 = 381.02 mhz 14 dbm each tone 10 db below p1db from 200 source lo leakage measured at mxip/mxin ?70 dbm measured at imxo, qmxo ?60 dbm demodulation bandwidth small signal 3 db bandwidth 75 mhz quadrature phase error lo = 380 mhz (loip/loin 760 mhz, single-ended) ?2 0.5 +2 degrees i/q amplitude imbalance 0.25 db noise figure (double sideband) from 200 source, f if = 380 mhz 21 db i/q baseband amplifier from iain to iopp/iopn and qain to qopp/ qopn, r load = 2 k, single-ended to ground gain 20 db bandwidth 10 pf differential load 125 mhz output dc offset (differential) lo leakage offset corrected using 500 pf capacitor on iofs, qofs (v iopp ? v iopn ) ?50 12 +50 mv output common-mode offset (v iopp + v iopn )/2 ? vcmo ?75 35 +75 mv group delay flatness 0 mhz to 50 mhz 3 ns p-p input-referred noise voltage frequency = 1 mhz 8 nv/hz output swing limit (upper) v s ?1 v output swing limit (lower) 0.5 v peak output current 1 ma input impedance 50||1 k||pf input bias current 2 a response from if and mx inputs to baseband amplifier output imxo and qmxo connected directly to iain and qain, respectively gain from mxip/mxin 30.5 db from ifip/ifin, vgin = 0.2 v 45.5 db from ifip/ifin, vgin = 1.2 v 1.5 db control input/outputs vcmo input range v s = 5 v 0.5 1 4 v v s = 2.7 v 0.5 1 1.7 v vref output voltage 0.95 1 1.05 v gain control voltage range vgin 0.2 1.2 v gain slope ?55 ?50 ?45 db/v gain intercept linear extrapolation back to theoretical gain at vgin = 0 v 55 61 67 db gain control input bias current 1 a lo inputs loip input return loss loin ac-coupled to ground (760 mhz applied to loip) ?6 db
ad8348 rev. a | page 5 of 28 parameter conditions min typ max unit power-up control enbl threshold low low = standby 0 v s /2 1 v enbl threshold high high = enable v s ? 1 v s /2 v s v input bias current 2 a power-up time time for final baseband amplifiers to be within 90% of final amplitude 45 s power-down time time for supply current to be <10% of enabled value 700 ns power supplies vpos1, vpos2, vpos3 voltage 2.7 5.5 v current (enabled) v s = 5 v, v enbl = 5 v 38 48 58 ma current (standby) v s = 5 v, v enbl = 0 v 75 a 1 these parameters are guaranteed but not tested in production. limits are 6 from the mean.
ad8348 rev. a | page 6 of 28 absolute maximum ratings table 2. parameter rating supply voltage on vpos1, vpos2, vpos3 pins 5.5 v lo input power 10 dbm (re: 50 ) if input power 18 dbm (re: 200 ) internal power dissipation 450 mw ja 68c/w maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +125c lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad8348 rev. a | page 7 of 28 pin configuration and fu nction descriptions loip 1 loin 28 vpos1 2 com1 27 iopn 3 qopn 26 iopp 4 qopp 25 vcmo 5 envg 24 iain 6 qain 23 com3 7 com3 22 imxo 8 qmxo 21 com2 9 vpos3 20 ifin 10 mxin 19 ifip 11 mxip 18 vpos2 12 vgin 17 iofs 13 qofs 16 vref 14 enbl 15 ad8348 top view (not to scale) 03678-002 figure 2. 28-lead tssop pin configuration table 3. pin function descriptions28-lead tssop pin no. mnemonic description equivalent circuit 1, 28 loip, loin lo inputs. for optimum performance, these inputs should be ac-coupled and driven differentially. differential drive from single-ended sources can be achieved via a balun. to obtain a broadband 50 input impedance, connect a 60.4 shunt resistor between loip and loin. typical input drive level is equal to ?10 dbm. a 2, 12, 20 vpos1, vpos2, vpos3 positive supply for lo, if, and biasing and baseband sections, respectively. these pins should be decoupled with 0.1 f and 100 pf capacitors. 3, 4, 25, 26 iopn, iopp, qopp, qopn i- and q-channel differential baseband outp uts. typical output swing is equal to 2 v p-p differential. the dc common-mode voltage level on these pins is set by the voltage on vcmo. b 5 vcmo baseband dc common-mode voltage. the voltage applied to this pin sets the dc common-mode levels for all the baseband outp uts and inputs (imxo, qmxo, iopp, iopn, qopp, qopn, iain, and qain). this pin can be connected either to vref or to a reference voltage from another device (typically an adc). c 6, 23 iain, qain i- and q-channel baseband amplifier inputs. the single-ended signals on these pins are referenced to vcmo and must have a dc bias equal to the dc voltage on the vcmo pin. if imxo (qmxo) is dc-coupled to iain (qain), biasing will be provided by imxo (qmxo). if an ac-coupled filter is placed between imxo and iain, these pins can be biased from the source driving vcmo through a 1 k resistor. the gain from iain/qain to the differential outputs (iopp/iopn an d qopp/qopn) is 20 db. d 7, 22 com3 ground for biasing and baseband sections. 8, 21 imxo, qmxo i- and q-channel mixer baseband outputs. these are low impedance (40 ) outputs whose bias levels are set by the voltage applied to th e vcmo pin. these pins are typically connected to iain and qain, respectively, either directly or through a filter. each output can drive a maximum current of 2.5 ma. h 9 com2 if section ground. 10, 11 ifin, ifip if inputs. ifin should be ac-coupled to grou nd. the single-ended if input signal should be ac-coupled into ifip. the nominal differen tial input impedance of these pins is 200 . for a broadband 50 input impedance, a minimum-loss l pad should be used; r series = 174 , r shunt = 57.6 . this provides a 200 source impedance to the if input. however, the ad8348 does not necessarily require a 200 source impedance, and a single shunt 66.7 resistor can be placed between ifip and ifin. e 13, 16 iofs, qofs i- and q-channel offset nulling inputs. dc offsets on the i-channel mixer output (imxo) can be nulled by connecting a 0.1 f capacitor from iofs to ground. driving iofs with a fixed voltage (typically a dac calibrated such that the offset at iopp/iopn is nulled) can extend the operating frequency range to include dc. the qofs pin can likewise be used to null offsets on the q-channel mixer output (qmxo). f 14 vref reference voltage output. this output voltage (1 v) is the main bias level for the device and can be used to externally bias the inp uts and outputs of the baseband amplifiers. the typical maximum drive current for this output is 2 ma. g
ad8348 rev. a | page 8 of 28 pin no. mnemonic description equivalent circuit 15 enbl chip enable input. active high. threshold is equal to v s /2. d 17 vgin gain control input. the voltage on this pin controls the gain on the if vga. the gain control voltage range is from 0.2 v to 1.2 v and corresponds to a conversion gain range from +25.5 db to ?18.5 db. this is the gain to the output of the mixers (that is, imxo and qmxo). there is an additional 20 db of fixed gain in the final baseband amplifiers (iain to iopp/iopn and qain to qopp/qopn). note that the gain control function has a negative sense (that is, increasing voltage decreases gain). d 18, 19 mxip, mxin auxiliary mixer inputs. if envg is low, the if ip and ifin inputs are disabled and mxip and mxin are enabled, allowing the vga to be bypassed. the auxiliary mixer inputs are fully differential inputs that should be ac-coupled to the signal source. i 24 envg active high vga enable. when envg is high, ifip and ifin inputs are enabled and mxip and mxin inputs are disabled. when envg is low, mxip and mxin inputs are enabled and ifip and ifin inputs are disabled. d 27 com1 lo section ground.
ad8348 rev. a | page 9 of 28 equivalent circuits loin loip com1 v pos1 03678-003 figure 3. circuit a vcmo v pos3 iopp, iopn, qopp, qopn com3 03678-004 figure 4. circuit b vcmo v pos3 com3 03678-005 figure 5. circuit c iain, qain, vgin, enbl, envg v pos3 com3 03678-006 figure 6. circuit d v pos2 com3 ifip ifin 03678-007 figure 7. circuit e iofs, qofs v pos3 com3 50a max 03678-008 figure 8. circuit f
ad8348 rev. a | page 10 of 28 v pos2 vref com2 03678-009 figure 9. circuit g v pos3 imxo, qmxo com3 03678-010 figure 10. circuit h v pos3 mxip mxin com3 03678-011 figure 11. circuit i
ad8348 rev. a | page 11 of 28 typical performance characteristics vga and demodulator vgin (v) v g a and mixer gain (db) linearity error (db) 0.2 0.3 0.4 ?20 ?5 ?10 ?15 10 5 0 30 25 20 15 ?6 ?3 ?4 ?5 0 ?1 ?2 4 3 2 1 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 03678-012 t = ?40c, v pos = 5v, freq = 380mhz linerr t = +85c, v pos = 5v, freq = 380mhz linerr t = +25c, v pos = 5v, freq = 380mhz linerr t = ?40c, v pos = 5v, freq = 380mhz t = +25c, v pos = 5v, freq = 380mhz t = +85c, v pos = 5v, freq = 380mhz figure 12. mixer gain and linearity error vs. vgin, v pos = 5 v, f if = 380 mhz, f bb = 1 mhz, temperature = ?40c, +25c, +85c vgin (v) v g a and mixer gain (db) linearity error (db) 0.2 0.3 0.4 ?25 ?10 ?15 ?20 5 0 ?5 25 20 15 10 ?6 ?3 ?4 ?5 0 ?1 ?2 4 3 2 1 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 03678-013 t = ?40c, v pos = 5v, freq = 900mhz t = +85c, v pos = 5v, freq = 900mhz linerr t = +85c, v pos = 5v, freq = 900mhz linerr t = +25c, v pos = 5v, freq = 900mhz linerr t = ?40c, v pos = 5v, freq = 900mhz t = +25c, v pos = 5v, freq = 900mhz figure 13. mixer gain and linearity error vs. vgin, v pos = 5 v, f if = 900 mhz, f bb = 1 mhz, temperature = ?40c, +25c, +85c vgin (v) v g a and mixer gain (db) linearity error (db) 0.2 0.3 0.4 ?20 ?5 ?10 ?15 10 5 0 30 25 20 15 ?6 ?3 ?4 ?5 0 ?1 ?2 4 3 2 1 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 03678-014 t = ?40c, v pos = 2.7v, freq = 380mhz t = +85c, v pos = 2.7v, freq = 380mhz linerr t = +85c, v pos = 2.7v, freq = 380mhz linerr t = ?40c, v pos = 2.7v, freq = 380mhz t = +25c, v pos = 2.7v, freq = 380mhz linerr t = +25c, v pos = 2.7v, freq = 380mhz figure 14. mixer gain and linearity error vs. vgin, v pos = 2.7 v, f if = 380 mhz, f bb = 1 mhz, temperature = ?40c, +25c, +85c vgin (v) v g a and mixer gain (db) linearity error (db) 0.2 0.3 0.4 ?25 ?10 ?15 ?20 5 0 ?5 25 20 15 10 ?6 ?3 ?4 ?5 0 ?1 ?2 4 3 2 1 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 03678-015 t = ?40c, v pos = 2.7v, freq = 900mhz t = +85c, v pos = 2.7v, freq = 900mhz linerr t = +85c, v pos = 2.7v, freq = 900mhz linerr t = +25c, v pos = 2.7v, freq = 900mhz linerr t = ?40c, v pos = 2.7v, freq = 900mhz t = +25c, v pos = 2.7v, freq = 900mhz figure 15. mixer gain and linearity error vs. vgin, v pos = 2.7 v, f if = 900 mhz, f bb = 1 mhz, temperature = ?40c, +25c, +85c if frequency (mhz) v g a and mixer gain (db) 100 18 20 22 24 26 28 200 300 400 500 600 700 800 900 1000 03678-016 2.7v, 0.2v, ?40c 5v, 0.2v, ?40c 2.7v, 0.2v, +25c 5v, 0.2v, +25c 2.7v, 0.2v, +85c 5v, 0.2v, +85c figure 16. gain vs. f if , vgin = 0.2 v, f bb = 1 mhz, temperature = ?40c, +25c, +85c if frequency (mhz) v g a and mixer gain (db) 100 ?30 ?25 ?20 ? 15 200 300 400 500 600 700 800 900 1000 03678-017 5v, 1.2v, ?40c 2.7v, 1.2v, ?40c 2.7v, 1.2v, +25 c 5v, 1.2v, +25 2.7v, 1.2v, +85 c 5v, 1.2v, +85 c c figure 17. gain vs. f if , vgin = 1.2 v, f bb = 1 mhz, temperature = ?40c, +25c, +85c
ad8348 rev. a | page 12 of 28 baseband frequency (mhz) v g a and mixer gain (db) 10 0 17 18 19 20 21 22 23 25 26 24 27 20 30 40 50 60 70 80 90 100 03678-018 2.7v, 0.2v, ?40c 5v, 0.2v, ?40c 2.7v, 0.2v, +25c 5v, 0.2v, +25c 2.7v, 0.2v, +85c 5v, 0.2v, +85c figure 18. gain vs. f bb , vgin = 0.2 v, f if = 380 mhz, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c baseband frequency (mhz) v g a and mixer gain (db) 10 0 ?26 ?23 ?20 ? 17 20 30 40 50 60 70 80 90 100 03678-019 2.7v, 1.2v, ?40c 5v, 1.2v, ?40c 2.7v, 1.2v, +25c 5v, 1.2v, +25c 2.7v, 1.2v, +85c 5v, 1.2v, +85c figure 19. gain vs. f bb , vgin = 1.2 v, f if = 380 mhz, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c vgin (v) input 1db compression point (dbm) (re 200 ? ) 0.30.2 ?25 ?10 ?15 ?20 5 0 ?5 15 10 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 03678-020 ?40c, 2.7v, 380mhz +25c, 5v, 380mhz +25c, 2.7v, 380mhz ?40c, 5v, 380mhz +85c, 5v, 380mhz +85c, 2.7v, 380mhz figure 20. input 1 db compression point (ip1db) vs. vgin, f if = 380 mhz, f bb = 1 mhz, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c vgin (v) input 1db compression point (dbm) (re 200 ? ) 0.30.2 ?20 ?5 ?10 ?15 10 5 0 20 15 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 03678-021 ?40c, 5v, 900mhz +85c, 5v, 900mhz +25c, 2.7v, 900mhz ?40c, 2.7v, 900mhz +85c, 2.7v, 900mhz +25c, 5v, 900mhz figure 21. input 1 db compression point (ip1db) vs. vgin, f if = 900 mhz, f bb = 1 mhz, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c if frequency (mhz) input iip3 (dbm) (re 200 ? ) 200 100 24 26 25 28 27 30 29 300 400 500 600 700 800 900 1000 03678-022 5v, 1.2v, ?40c 2.7v, 1.2v, ?40c 2.7v, 1.2v, +25c 5v, 1.2v, +25c 2.7v, 1.2v, +85c 5v, 1.2v, +85c figure 22. iip3 vs. f if , vgin = 1.2 v, f bb = 1 mhz, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c, tone spacing = 20 khz if frequency (mhz) input iip3 (dbm) (re 200 ? ) 100 200 ?15 ?10 ?5 0 300 400 500 600 700 800 900 1000 2.7v, 0.2v, ?40c 2.7v, 0.2v, +25c 2.7v, 0.2v, +85c 5v, 0.2v, +25c 5v, 0.2v, +85c 5v, 0.2v, ?40c 03678-023 figure 23. iip3 vs. f if , vgin = 0.2 v, f bb = 1 mhz, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c
ad8348 rev. a | page 13 of 28 baseband frequency (mhz) v g a and mixer input iip3 (dbm) (re 200 ? ) 10 02 0 22 26 24 28 30 32 30 40 50 60 70 80 90 100 5v, 1.2v, +25c 5v, 1.2v, ?40c 2.7v, 1.2v, +25c 5v, 1.2v, +85c 2.7v, 1.2v, ?40c 2.7v, 1.2v, +85c 03678-024 figure 24. iip3 vs. f bb , vgin = 1.2 v, f if = 380 mhz, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c baseband frequency (mhz) v g a and mixer input iip3 (dbm) (re 200 ? ) 10 02 0 ?20 ?15 ?10 ?5 0 30 40 50 60 70 80 90 100 5v, 0.2v, +25c 5v, 0.2v, ?40c 2.7v, 0.2v, ?40c 03678-025 5v, 0.2v, +85c 2.7v, 0.2v, +85c 2.7v, 0.2v, +25c figure 25. iip3 vs. f bb , vgin = 0.2 v, f if = 380 mhz, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c if frequency (mhz) noise figure (db) 15050 250 8 9 10 11 12 13 14 15 16 350 450 550 650 750 850 950 03678-026 nf vgin = 0.2v figure 26. noise figure vs. f if , t = 25c, vgin = 0.2 v, f bb = 1 mhz vgin (v) noise figure (db) input iip3 (dbm) (re 200 ? ) 0.2 0.3 0.4 0 15 10 5 30 25 20 45 40 35 ?10 5 0 ?5 15 10 35 30 25 20 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 03678-027 nf iip3 figure 27. noise figure and iip3 vs. vgin, temperature = 25c, f if = 380 mhz, f bb = 1 mhz, v pos = 2.7 v vgin (v) noise figure (db) input iip3 (dbm) (re 200 ? ) 0.2 0.3 0.4 0 15 10 5 30 25 20 40 35 ?10 5 0 ?5 15 10 35 30 25 20 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 03678-028 nf iip3 figure 28. noise figure and iip3 vs. vgin, temperature = 25c, f if = 380 mhz, f bb = 1 mhz, v pos = 5 v lo input level (v) noise figure (db) phase error (degrees) ?12 ?10 8 11 10 9 14 13 12 16 15 ?2.0 ?0.5 ?1.0 ?1.5 0 2.0 1.5 1.0 0.5 ?8 ?6 ?4 ?2 0 03678-029 nf @ lo = 50mhz nf @ lo = 380mhz nf @ lo = 900mhz phase error 50mhz phase error 380mhz phase error 900mhz figure 29. noise figure and quadrature phase error imxo/qmxo vs. lo input level, temperature = 25c, vgin = 0.2 v, v pos = 5 v for f if = 50 mhz, 380 mhz, and 900 mhz
ad8348 rev. a | page 14 of 28 demodulator using mxip and mxin if frequency (mhz) mixer gain (db) 100 200 8.5 8.0 10.0 9.5 9.0 11.0 10.5 300 400 500 600 700 800 900 1000 03678-030 temp = ?40c, v pos = 5v temp = +25c, v pos = 5v temp = +85c, v pos = 2.7v temp = +85c, v pos = 5v temp = ?40c, v pos = 2.7v temp = +25c, v pos = 2.7v figure 30. mixer gain vs. f if , v pos = 2.7 v, 5 v, f bb = 1 mhz, temperature = ?40c, +25c, +85c if frequency (mhz) mixer input p1db (dbm) (re 200 ? ) 100 200 ?8.0 ?6.5 ?7.0 ?7.5 ?3.0 ?2.5 ?2.0 ?3.5 ?4.0 ?4.5 ?5.0 ?5.5 ?6.0 ? 1.5 300 400 500 600 700 800 900 1000 03678-031 temp = ?40c, v pos = 2.7v temp = ?40c, v pos = 5v temp = +25c, v pos = 2.7v temp = +25c, v pos = 5v temp = +85c, v pos = 2.7v temp = +85c, v pos = 5v figure 31. input 1 db compression point vs. f if , f bb = 1 mhz, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c if frequency (mhz) input iip3 (dbm) (re 200 ? ) 50 150 10 14 21.0 13 12 11 17 16 15 18 250 350 450 550 650 750 850 950 03670-032 iip3 2.7v iip3 5v nf 2.7v nf 5v noise figure (db) 19.0 20.5 20.0 19.5 23.0 22.5 22.0 21.5 figure 32. iip3 and noise figure vs. f if , v pos = 2.7 v, 5 v, temperature = 25c
ad8348 rev. a | page 15 of 28 final baseband amplifiers baseband frequenc y (mhz) gain (db) 0.1 14 13 17 16 15 20 19 18 21 1 10 100 1000 03678-033 +25c, 5v +85c, 2.7v ?40c, 5v +25c, 2.7v ?40c, 2.7v +85c, 5v figure 33. gain vs. f bb , v vcmo = vref = 1 v, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c baseband frequenc y (mhz) op1db (dbv) 0.1 ?15 ?20 ?10 0 ?5 5 1 10 100 1000 03678-034 +25c, 5v +85c, 5v +25c, 2.7v ?40c, 2.7v +85c, 2.7v ?40c, 5v figure 34. op1db compression vs. f bb , v vcmo = vref = 1 v, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c baseband frequenc y (mhz) oip3 (dbv) 10 ?10 10 15 20 25 30 ?15 ?5 0 5 35 50 70 90 30 130110 150 170 190 03678-035 ?40c, 2.7v +25c, 2.7v ?40c, 5v +25c, 5v +85c, 5v +85c, 2.7v figure 35. oip3 vs. f bb , v vcmo = vref = 1 v, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c frequency (khz) baseband amplifier input noise spectral density (nv/ hz) 1 1 5 6 7 8 9 0 2 3 4 10 10 100 1000 10000 100000 03678-036 figure 36. noise spectral density
ad8348 rev. a | page 16 of 28 vga/demodulator and baseband amplifier if frequency (mhz) quadr a ture phase error (degrees) 100 ?1.5 0 0.5 1.0 1.5 ?2.0 ?1.0 ?0.5 2.0 200 300 400 500 600 700 800 900 1000 03678-037 2.7v, 0.2v, ?40c 2.7v, 0.2v, +25c 5v, 0.2v, ?40c 2.7v, 0.2v, +85c 5v, 0.2v, +25c 5v, 0.2v, +85c figure 37. quadrature phase error vs. f if , vgin = 0.7 v, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c baseband frequency (mhz) quadr a ture phase error (degrees) ?1.5 0 0.5 1.0 1.5 ?2.0 ?1.0 ?0.5 2.0 5 0 10152025303540 03678-038 5v, 0.7v, +85c 2.7v, 0.7v, +85c 2.7v, 0.7v, ?40c 5v, 0.7v, ?40c 2.7v, 0.7v, +25c 5v, 0.7v, +25c figure 38. quadrature phase error vs. f bb , vgin = 0.7 v, v pos = 2.7 v, 5 v, temperature = ?40c, +25c, +85c, f if = 380 mhz baseband frequency (mhz) i/q amplitude mism a tch (db) ?0.4 ?0.2 0 0.2 0.4 5 0 10152025303540 03678-039 5v, 0.7v, 25c figure 39. i/q amplitude imbalance vs. f bb , temperature = 25c, v pos = 5 v if frequency (mhz) i/q amplitude mism a tch (db) ?1.5 0 0.5 1.0 1.5 ?2.0 ?1.0 ?0.5 2.0 200 100 300 400 500 600 700 800 900 1000 03678-040 figure 40. i/q amplitude imbalance vs. f if , temperature = 25c, v pos = 5 v if frequency (mhz) shunt resistance ( ? ) shunt capacitance (pf) 50 150 250 100 160 140 120 220 200 180 300 280 260 240 0.2 0.8 0.6 0.4 1.4 1.2 1.0 2.2 2.0 1.8 1.6 350 450 550 650 750 850 950 03678-041 shunt capacitance shunt resistance figure 41. input impedance of if input vs. f if , vgin = 0.7 v, v pos = 5 v 0 180 30 330 60 90 270 300 120 240 150 210 impedance circle ifip with l pad ifip without l pad 03678-042 figure 42. s11 of if input vs. f if , f if = 50 mhz to 1 ghz, vgin = 0.7 v, v pos = 5 v (with l pad, with no pad, normalized to 50 )
ad8348 rev. a | page 17 of 28 if frequency (mhz) shunt resistance ( ? ) shunt capacitance (pf) 50 100 150 200 100 160 140 120 220 200 180 300 280 260 240 0 0.5 2.5 2.0 1.5 1.0 250 300 350 400 450 550 650 750 850 950 500 600 700 800 900 1000 03678-043 (shunt capacitance) (shunt resistance) figure 43. input impedance of mixer input vs. f if , vgin = 0.7 v, v pos = 5 v 0 180 30 330 60 90 270 300 120 240 150 210 impedance circle mx inputs with 4:1 balun mxip input pin 03678-044 figure 44. s11 of mixer input vs. f if , f if = 50 mhz to 1 ghz, vgin = 0.7 v, v pos = 5 v (with and without balun) external lo frequency (mhz) return loss (db) ?30 ?15 ?10 ?5 ?35 ?25 ?20 0 400 500 200 100 300 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 03678-045 return loss loip pin single-ended, loin ac-coupled to ground. figure 45. return loss of loip input vs. external lo frequency frequency applied to loip/loin (mhz) return loss (db) ?20 ?15 ?10 ?5 ?35 ?30 ?25 0 400 500 200 100 300 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 03678-046 return loss lo input, through balun with 60.4 ? in shunt between loip/loin figure 46. return loss of lo in put vs. external lo frequency through balun, with termination resistor temperature (c) supply current (ma) 50 55 60 35 40 45 65 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 70 80 03678-047 v s = 5v v s = 2.7v figure 47. supply current vs. temperature
ad8348 rev. a | page 18 of 28 theory of operation divide by 2 phase splitter loin loip imx o vcmo vref vcmo iof s iain iopp iopn vcmo qofs envg qxmo mxin mxip qain qopp qopn gain control bias cell ifip ifin vgin enbl v ref 03678-049 18 24 19 21 16 23 25 26 28 1 5 3 4 6 13 8 14 15 11 10 17 ad8348 figure 48. functional block diagram vga the vga is implemented using the patented x-amp architecture. the single-ended if signal is attenuated in eight discrete 6 db steps by a passive r-2r ladder. each discrete attenuated version of the if signal is applied to the input of a transconductance stage. the current outputs of all transconductance stages are summed together and drive a resistive load at the output of the vga. gain control is achieved by smoothly turning on and off the relevant transconductance stages with a temperature- compensated interpolation circuit. this scheme allows the gain to continuously vary over a 44 db range with linear-in-decibel gain control. this configuration also keeps the relative dynamic range constant (for example, iip3 ? nf in db) over the gain setting; however, the absolute intermodulation intercepts and noise figure vary directly with gain. the analog voltage vgin sets the gain. vgin = 0.2 v is the maximum gain setting, and vgin = 1.2 v is the minimum voltage gain setting. downconversion mixers the output of the vga drives two (i and q) double-balanced gilbert cell downconversion mixers. alternatively, driving the envg pin low can disable the vga, and the mixers can be externally driven directly via the mxip and mxin ports. at the input of the mixer, a degenerated differential pair performs linear voltage-to-current conversions. the differential output current feeds into the mixer core where it is downconverted by the mixing action of the gilbert cell. the phase splitter provides quadrature lo signals that drive the lo ports of the in-phase and quadrature mixers. buffers at the output of each mixer drive the imxo and qmxo pins. these linear, low output impedance buffers drive 40 , temperature-stable, passive resistors in series with each output pin (imxo and qmxo). this 40 should be considered when calculating the reverse termination if an external filter is inserted between imxo (qmxo) and iain (qain). the vcmo pin sets the dc output level of the buffer. this can be set externally or connected to the on-chip 1.0 v reference, vref. phase splitter quadrature generation is achieved using a divide-by-2 frequency divider. unlike a polyphase filter that achieves quadrature over a limited frequency range, the divide-by-2 approach maintains quadrature over a broad frequency range and does not attenuate the lo. the user, however, must provide an external signal xlo that is twice the frequency of the desired lo frequency. xlo drives the clock inputs of two flip-flops that divide down the frequency by a factor of 2. the outputs of the two flip-flops are one-half period of xlo out of phase. equivalently, the outputs are one- quarter period (90) of the desired lo frequency out of phase. because the transitions on xlo define the phase difference at the outputs, deviation from 50% duty cycle translates directly to quadrature phase errors. if the user generates xlo from a 1 frequency (f ref ) and a frequency-doubling circuit (xlo = 2 f ref ), fundamentally there is a 180 phase uncertainty between f ref and the ad8348 internal quadrature lo. the phase relationship between i and q lo, however, is always 90. i/q baseband amplifiers two (i and q) fixed gain (20 db), single-ended-to-differential amplifiers are provided to amplify the demodulated signal after off-chip filtering. the amplifiers use voltage feedback to linearize the gain over the demodulation bandwidth. these amplifiers can be used to maximize the dynamic range at the input of an adc following the ad8348. the input to the baseband amplifiers, iain (qain), feeds into the base of a bipolar transistor with an input impedance of roughly 50 k. the baseband amplifiers sense the single-ended difference between iain (qain) and vcmo. iain (qain) can be dc biased by terminating it with a shunt resistor to vcmo, such as when an external filter is inserted between imxo (qmxo) and iain (qain). alternatively, any dc connection to imxo (qxmo) can provide appropriate bias via the offset-nulling loop. enable a master biasing cell that can be disabled using the enbl pin controls the biasing for the chip. if the enbl pin is held low, the entire chip powers down to a low power sleep mode, typically consuming 75 a at 5 v. baseband offset cancellation a low output current integrator senses the output voltage offset at iopp and iopn (qopp and qopn) and injects a nulling current into the signal path. the integration time constant of the offset-nulling loop is set by capacitor cofs from iofs (qofs) to
ad8348 rev. a | page 19 of 28 vcmo. this forms a high-pass response for the baseband signal path with a lower 3 db frequency of cofs f pass ? = 26502 1 alternatively, the user can externally adjust the dc offset by driving iofs (qofs) with a digital-to-analog converter or other voltage source. in this case, the baseband circuit operates all the way down to dc ( f pass = 0 hz). the integrator output current is only 50 a and can be easily overridden with an external voltage source. the nominal voltage level applied to iofs (qofs) to produce a 0 v differential offset at the baseband outputs is 900 mv. the iofs (qofs) pin must be connected to either a bypass capacitor (>0.1 f) or an external voltage source to prevent the feedback loop from oscillating. the feedback loop will be broken at dc if an ac-coupled baseband filter is placed between the mixer outputs and the baseband amplifier inputs. if an ac-coupled filter is implemented, the user must handle the offset compensation via some external means.
ad8348 rev. a | page 20 of 28 applications basic connections figure 49 shows the basic connections schematic for the ad8348. c32 1000pf c31 1000pf r31 57.6 ? 13 54 j21 lo c21 1000pf c22 1000pf r21 60.4 ? +v s c0q 0.1f c11 4.7f ifip r32 174? t21 etc1-1-13 ifip mxip vpos2 vgin iofs qofs vref enbl loin loip vpos1 com1 iopn qopn iopp qopp vcmo envg iain qain com3 com3 imxo qmxo com2 vpos3 ifin mxin ad8348 c0l 0.1f j2i iopp j3i iop n j2q qopp j3q qopn c53 100pf c54 0.1f +v s c51 100pf c52 0.1f +v s v ref sw12 +v s if mx sw11 +v s enbl denbl c55 100pf c56 0.1f vgin mxip r42 0 ? t41 etk4-2t c41 1f c43 1000pf c42 1000pf 03678-064 18 17 16 15 28 27 26 25 24 23 22 21 20 19 11 12 13 14 1 2 3 4 5 6 7 8 9 10 figure 49. basic connections schematic power supply the voltage supply for the ad8348, between 2.7 v and 5 v, should be provided to the +vposx pins, and ground should be connected to the comx pins. each supply pin should be decoupled separately using two capacitors whose recommended values are 100 pf and 0.1 f (values close to these can also be used). device enable to enable the device, the enbl pin should be driven to v s . grounding the enbl pin disables the device. vga enable driving the voltage on the envg pin to v s enables the vga. in this mode, the mx inputs are disabled and the if inputs are used. grounding the envg pin disables the vga and the if inputs. when the vga is disabled, the mx inputs should be used. gain control when the vga is enabled, the voltage applied to the vgin pin sets the gain. the gain control voltage range is between 0.2 v and 1.2 v. this corresponds to a gain range between +25.5 db and ?18.5 db. lo inputs for optimum performance, the local oscillator port should be driven differentially through a balun. the recommended balun is m/a-com etc1-1-13. the lo inputs to the device should be ac-coupled, unless an ac-coupled transformer is being used. for a broadband match to a 50 source, a 60.4 resistor should be placed between the loip and lion pins. 1 28 loip loin 60.4 ? 31 45 1000pf 1000pf etc1-1-13 lo 03678-050 figure 50. differential lo drive with balun alternatively, the lo port can be driven from a single-ended source without a balun ( figure 51 ). the lo signal is ac-coupled directly into the loip pin via an ac-coupling capacitor, and the loin pin is ac-coupled to ground. driving the lo port from a single- ended source results in an increase in both quadrature phase error and lo leakage. 1 28 loip loin 60.4 ? 1000pf 1000pf lo 03678-051 figure 51. single-ended lo drive the recommended lo drive level is between ?12 dbm and 0 dbm. the lo frequency at the input to the device should be twice that of the desired lo frequency at the mixer core. the applied lo frequency range is between 100 mhz and 2 ghz. if inputs the if inputs have an input impedance of 200 . a broadband 50 match can be presented to the driving source through the use of a minimum-loss l pad. this minimum-loss pad introduces an 11.46 db loss in the input path and must be taken into account when calculating metrics such as gain and noise figure. figure 42 shows the s11 of the if input with and without the l pad. 11 10 1000pf 1000pf 174 ? 57.6 ? ifip ifip ifin 03678-052 figure 52. minimum-loss l pad for 50 if input mx inputs the mixer inputs, mxip and mxin, have a nominal impedance of 200 and should be driven differentially. when driven from a differential source, the input should be ac-coupled to the source via capacitors, as shown in figure 53 .
ad8348 rev. a | page 21 of 28 18 19 1000pf 1000pf mxip mxip mxin mxin 03678-053 figure 53. driving the mx inputs from a differential source if the mx inputs are to be driven from a single-ended 50 source, a 4:1 balun can be used to transform the 200 impedance of the inputs to 50 while performing the required single-ended- to-differential conversion. the recommended transformer is the m/a-com etk4-2t. 03678-066 mxip 1000pf 1000pf etk4-2t 1f mxip mxin 18 19 figure 54. driving the mx inputs from a single-ended 50 source baseband outputs the baseband amplifier outputs, iopp, iopn, qopp, and qopn, should be presented with loads of at least 2 k (single-ended to ground). they are not designed to drive 50 loads directly. the typical swing for these outputs is 2 v p-p differential (1 v p-p single-ended), but larger swings are possible as long as care is taken to ensure that the signals remain within the lower limit of 0.5 v and the upper limit of v s ? 1 v of the output swing. to achieve a larger swing, it is necessary to adjust the common-mode bias of the baseband output signals. increasing the swing can have the benefit of improving the signal-to-noise ratio of the baseband amplifier output. when connecting the baseband outputs to other devices, care should be taken to ensure that the outputs are not capacitively loaded by approximately 20 pf or more. such loads could potentially overload the output or induce oscillations. the effect of capacitive loading on the baseband amplifier outputs can be mitigated by inserting series resistors of approximately 200 . output dc bias level the dc bias of the mixer outputs and the baseband amplifier inputs and outputs is determined by the voltage that is driven onto the vcmo pin. the range of this voltage is typically between 500 mv and 4 v when operating with a 5 v supply. to achieve maximum voltage swing from the baseband amplifiers, vcmo should be driven at 2.25 v; this allows a swing of up to 7 v p-p differential (3.5 v p-p single-ended). interfacing to detector for agc operation the ad8348 can be interfaced with a detector such as the ad8362 rms-to-dc converter to provide an automatic signal- leveling function for the baseband outputs. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1000pf 1000pf 13 54 l o 1000pf 1000pf 60.4 ? 1:1 ad8348 100pf 0.1f +v s v ref +v s +v s 100pf 100pf v ref 1000pf 100pf 1000pf 1f 1f 1f 1f 100pf 0.1f 1f 1000pf +v s 0.1f 100pf +v s 0.1f 100pf v cmo v set +v s ad8362 acom comm vtgt decl vpos inhi vout inlo acom pwdn clpf comm vref chpf vset decl to baseband q adc to baseband i adc if input z o = 200 ? 1.02k ? 1.24k ? 03678-0-055 ifip mxip vpos2 vgin iofs qofs vref enbl loin loip vpos1 com1 iopn qopn iopp qopp vcmo envg iain qain com3 com3 imxo qmxo com2 vpos3 ifin mxin 18 17 16 15 28 27 26 25 24 23 22 21 20 19 11 12 13 14 1 2 3 4 5 6 7 8 9 10 figure 55. ad8362 config uration for agc operation assuming the i and q channels have the same rms power, the mixer output (or the output of the baseband filter) of one channel can be used as the input of the ad8362. the ad8362 should be operated in a region where its linearity error is small. also, a voltage divider should be implemented with an external resistor in series with the 200 input impedance of the ad8362 input. this attenuates the ad8348 mixer output so that the ad8362 input is not overdriven. the size of the resistor between the mixer output and the ad8362 input should be chosen so that the peak signal level at the input of the ad8362 is about 10 db less than the approximately 10 dbm maximum of the ad8362 dynamic range. the other side of the ad8348 baseband output should be loaded with a resistance equal to the series resistance of the attenuating resistor in series with the ad8362s 200 input impedance. this resistor should be tied to the source driving vcmo so that there is no dc drawn from the mixer output.
ad8348 rev. a | page 22 of 28 the level of the mixer output (or the output of the baseband filter) can then be set by varying the setpoint voltage fed to pin 11 (vset) of the ad8362. care should be taken to ensure that blockersunwanted signals in the band of interest that are demodulated along with the desired signaldo not dominate the rms power of the ad8362 input. this can cause an undesired reduction in the level of the mixer output. to overcome this, baseband filtering can be implemented to filter out undesired signals before the signal is presented to the ad8362. figure 56 shows the effectiveness of the agc loop in maintaining a baseband amplifier output amplitude with less than 0.5 db of amplitude error ov er an if input range of 40 db while demodulating a qpsk-mod ulated signal at 380 mhz. the ad8362 is insensitive to cr est factor variations and therefore provides similar pe rformance regardless of the modulation of the incoming signal. ifip power input (dbm, z o = 200 ? ) i channel vol t age output (iopp ? iopn) (mv rms) error (db) ?55 ?45 70 90 80 120 110 100 140 130 ?4 ?2 ?3 1 0 ?1 3 2 ?35 ?25 ?15 ?5 5 qpsk error 03678-065 ?5.1dbm re 10k ? figure 56. ad8348 baseband amplifier output vs. if input power with ad8362 agc loop baseband filters baseband low-pass or band-pass filtering can be conveniently performed between the mixer outputs (imxo and qmxo) and the input to the baseband amplifiers. consideration should be given to the output impedance of the mixers (40 ). l2 1.2h ad8348 imxo vcmo iain r1 60? l1 0.68h c5 150pf c6 82pf r2 100? c1 4.7pf c2 8.2pf 03678-056 to ad8362 input if agc loop is used figure 57. baseband filter schematic figure 57 shows the schematic for a 100 , fourth-order elliptic low-pass filter with a 3 db cutoff frequency of 20 mhz. source and load impedances of approximately 100 ensure that the filter sees a matched source and load. this also ensures that the mixer output is driving an overall load of 200 . note that the shunt termination resistor is tied to the source driving vcmo and not to ground. this ensures that the input to the baseband amplifier is biased to the proper reference level. vcmo is not an output pin and must be biased by a low impedance source. the frequency response and group delay of this filter are shown in figure 58 and figure 59 . frequency (mhz) a ttenu a tion (db) 1 ?80 ?50 ?40 ?60 ?70 ?30 ?20 ?10 0 10 100 03678-057 figure 58. baseband filter response frequency (mhz) group del a y (ns) 1 0 15 20 10 5 25 30 35 40 45 50 10 100 03678-058 1 2 figure 59. baseband filter group delay
ad8348 rev. a | page 23 of 28 lo generation analog devices has a line of plls that can be used for generating the lo signal. tabl e 4 lists the plls and their maximum frequency and phase noise performance. table 4. adi pll selection table adi model frequency f in (mhz) @ 1 khz n dbc/hz, 200 khz pfd adf4001bru 165 ?99 adf4001bcp 165 ?99 adf4110bru 550 ?91 adf4110bcp 550 ?91 adf4111bru 1200 ?78 adf4111bcp 1200 ?78 adf4112bru 3000 ?86 adf4112bcp 3000 ?86 adf4116bru 550 ?89 adf4117bru 1200 ?87 adf4118bru 3000 ?90 adi also offers the adf4360 fully integrated synthesizer and vco on a single chip that offers differential outputs for driving the local oscillator input of the ad8348. this means that the user can eliminate the use of a balun for single-ended-to-differential conversions. the adf4360 comes as a family of chips with six operating frequency ranges. one can be chosen depending on the local oscillator frequency required. table 5 shows the options available. table 5. adf4360 family operating frequencies adi model output frequency range (mhz) adf4360-1 2150 to 2450 adf4360-2 1800 to 2150 adf4360-3 1550 to 1950 adf4360-4 1400 to 1800 adf4360-5 1150 to 1400 adf4360-6 1000 to 1250 adf4360-7 lower frequencies set by external l evaluation board figure 60 shows the schematic for the ad8348 evaluation board. note that uninstalled components are indicated with the open designation. the board is powered by a single supply in the range of 2.7 v to 5.5 v. table 6 details the various configu- ration options of the evaluation board. table 7 shows the various jumper configurations for operating the evaluation board with different signal paths. power to operate the board can be fed to a single v s test point located near the lo input port at the top of the evaluation board. a gnd test point is conveniently provided next to the v s test point for the return path. the device is enabled by moving switch sw11 (at the bottom left of the evaluation board) to the enbl position. the device is disabled by moving sw11 to the denbl position. if desired, the device can be enabled and disabled from an external source that can be fed into the enbl sma connector or the venb test point, in which case sw11 should be placed in the denbl position. the if and mx inputs are selected via sw12. the switch should be moved in the direction of the desired input. gain control for convenience, a potentiometer, r15, is provided to allow for changes in gain without the need for an additional dc voltage source. to use the potentiometer, the sw13 switch must be set to the pot position. alternatively, an external voltage applied to either the test point or sma connector labeled vgin can set the gain. sw13 must be set to the ext position when an external gain control voltage is used. lo input the local oscillator signal should be fed to the sma connector j21. this port is terminated in 50 . the acceptable lo power input range is from ?12 dbm to 0 dbm and must be at a frequency double that of the if/mx frequency. remember that the ad8348 uses a 2:1 frequency divider in the lo path to generate the internally required quadrature-phase-related lo signals. if input the if input should be fed into the sma connector ifip. the vga must be enabled when this port is used (sw12 in the if position). when this if input is chosen, the signal path includes a minimum-loss attenuator to transform a 50 input source to the 200 source impedance level for which the vga was designed. this pad provides a very broadband input match at the expense of an 11.46 db power attenuation in the input path. it is very important to take this into account when measuring the noise and distortion performance of the unmodified board using the ifip input; the apparent noise figure will be degraded by 11.46 db, and the apparent iip3 will be 11.46 db higher than actual. if full weak-signal performance is desired from the evaluation board, the attenuator (comprising r31 and r32) should be removed and replaced with a low-loss rf transformer providing the desired 4:1 impedance ratio. when a transformer is used, ifin should be ac-coupled to ground and not driven differentially with ifip. mx input the evaluation board is by default set for a differential mx drive through a balun (t41) from a single-ended source fed into the mxip sma connector. when the mx inputs are used, the internal vga is bypassed. to change to a differential driving source, t41 should be removed along with resistor r42. the 0 r43 and r44 resistors should be installed in place of t41 to bridge the gap between the input traces. this presents a nominal
ad8348 rev. a | page 24 of 28 differential impedance of 200 (100 per side). the differential inputs should then be fed into sma connectors mxip and mxin. mixer outputs the i and q mixer outputs are available through the imxo and qmxo sma connectors. these outputs are biased to vcmo and are not designed to drive loads smaller than 200 . to prevent damage to test equipment that cannot tolerate dc biases, pads for series dc-blocking capacitors are provided. these pads are populated with 0 by default. baseband outputs the baseband outputs are made available at the iopp, iopn, qopp, and qopn test points and sma connectors. these outputs are not designed to be connected directly to 50 loads and should be presented with loads of approximately 2 k or greater. the dc bias level of the baseband amplifier outputs are by default tied to vref through lk11. if desired, the dc bias level can be changed by removing lk11 and driving a dc voltage onto the vcmo test point. l3i open l2i open l1i open r2i open r1i open c7i open c6i open c5i open c4i open c3i open c2i open c1i open lk2i vcmo j1i imxo c13 0.1f lk1i vcmo lk11 lk4i lk3i c10i 0 ? c32 1000pf c31 1000pf r31 57.6 ? 13 54 j21 lo c21 1000pf c22 1000pf r21 60.4 ? +v s c51 100pf c52 0.1f +v s c53 100pf c54 0.1f +v s mxin mxip r42 0 ? r44 open r43 open c42 1000pf c43 1000pf sw13 c12 0.1f r13 open j3i iopn j2i iopp r5i 0 ? r4i 0 ? iopn iopp gnd c9i open c8i open c0i 0.1f c0q 0.1f c11 4.7f ifip ext pot r14 10k? lk5i lk5q +v s iofs qofs enbl venb r3i 49.9 ? r12 10k? r11 49.9 ? enbl denbl sw11 vref r32 174? t21 etc1-1-13 ad8348 imxo l3q open l2q open l1q open r2q open r1q open c7q open c6q open c5q open c4q open c3q open c2q open c1q open lk2q vcmo vcmo j1q qmxo lk1q lk4q lk3q c10q 0 ? r3q 49.9 ? qmxo sw12 j3q qopn j2q qopp r5q 0 ? r4q 0 ? qopn qopp gnd gnd c9q open c8q open +v s if mx c55 100pf c55 0.1f r41 open vgin r15 10k? pot t41 etk4-2t c41 1f 03678-059 ifip mxip vpos2 vgin iofs qofs vref enbl loin loip vpos1 com1 iopn qopn iopp qopp vcmo envg iain qain com3 com3 imxo qmxo com2 vpos3 ifin mxin 18 17 16 15 28 27 26 25 24 23 22 21 20 19 11 12 13 14 1 2 3 4 5 6 7 8 9 10 figure 60. evaluation board schematic
ad8348 rev. a | page 25 of 28 03678-060 figure 61. evaluation board top layer 03678-061 figure 62. evaluation board top silkscreen
ad8348 rev. a | page 26 of 28 03678-062 figure 63. evaluation board bottom layer 03678-063 figure 64. evaluation board bottom silkscreen
ad8348 rev. a | page 27 of 28 table 6. evaluation board configuration options component function default condition v s , gnd power supply and ground vector pins. not applicable sw11, enbl device enable: place sw11 in the enbl position to connect the enbl pin to v s . place sw11 in the denbl position to disable the device by gr ounding the pin enbl through a 50 pull-down resistor. the device can also be enabled via an external voltage applied to enbl or venb. sw11 = enbl sw13, r15, vgin gain control selection: with sw13 in the pot posit ion, the gain of the vga can be set using the r15 potentiometer. with sw13 in the ext position, the vga gain can be set by an external voltage to the sma connector vgin. for vga operation, the vga must first be enabled by setting sw12 to the if position. sw13 = pot sw12 vga enable selection: with sw12 in the if position, the envg pin is connected to v s and the vga is enabled. the if input should be used wh en sw12 is in the if position. with sw12 in the mx position, the envg pin is grounded and the vg a is disabled. the mx inputs should be used when sw12 is in the mx position. sw12 = if ifip, r31, r32 if inputs: the single-ended if signal should be connected to this sma connector. r31 and r32 form an l pad that presents a 50 termination to the driving source. this l pad introduces an 11.46 db loss in the input signal path and should be taken into consideration when calculating the gain of the ad8348. r31 = 57.6 r32 = 174 mxip, mxin, t41, r41, r42, c42, c43 mixer inputs: these inputs can be configured for either differential or single-ended operation. the evaluation board is by default set for diff erential mx drive through a balun (t41) from a single-ended source fed into the mxip sma connect or. to change to a differential driving source, t41 should be removed along with resistor r42. th e 0 resistors r43 and r44 should be installed in place of t41 to bridge the gap between the input traces. this will present a nominal differential impedance of 200 (100 per side). the differential inputs should then be fed into sma connectors mxip and mxin. t41 = m/a-com etk4-2t; r41= open; c42, c43 = 1000 pf; r42 = 0 lk11, vcmo baseband amplifier output bias: installing lk11 connects vref to vcmo. this sets the bias level on the baseband amplifiers to vref, which is eq ual to approximately 1 v. alternatively, with lk11 removed, the bias level of the baseband amplifiers can be set by applying an external voltage to the vcmo test point. lk11 installed c8, c9, r4, r5 (i and q) baseband amplifier outputs and outp ut filter: additional low-pass filtering can be provided at the baseband output with these filters. r4, r5 = 0 c10 (i and q) mixer output dc-blocking capacitors: the mixer outputs are biased to vcmo. to prevent damage to test equipment that cannot tolerate dc biases, c10 is provided to block the dc component, thus protecting the test equipment. c10 = 0 c1 to c7, r1, r2, l1 to l3 (i and q) baseband filter: these components are provided for baseband filtering between the mixer outputs and the baseband amplif ier inputs. the baseband amplifier input impedance is high and the filter termination impedance is set by r2. see table 7 for the jumper settings. all = open lk5 (i and q) offset compensation loop disable: installing these jumpers will disable the offset compensation loop for the corresponding channel. lk5x = open table 7. filter-jumper configuration options condition lk1x lk2x lk3x lk4x xmxo to xain directly ? ? xmxo to xain via filter ? ? xmxo to j1x directly, xain unused ? ? xmxo to j1x via filter, xain unused ? ? drive xain from j1x ?
ad8348 rev. a | page 28 of 28 outline dimensions 28 15 14 1 8 0 compliant to jedec standards mo-153ae seating plane coplanarity 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 65. 28-lead thin shrink small outline package [tssop] (ru-28) dimensions shown in millimeters ordering guide model temperature range package description package option ad8348aru ?40c to +85c 28-lead thin shrink small outline package [tssop] ru-28 ad8348aru-reel7 ?40c to +85c 28-lead thin shrink sm all outline package [tssop] 7 tape and reel ru-28 ad8348aruz 1 ?40c to +85c 28-lead thin shrink small outline package [tssop] ru-28 AD8348ARUZ-REEL7 1 ?40c to +85c 28-lead thin shrink small outl ine package [tssop] 7 tape and reel ru-28 ad8348-eval evaluation board 1 z = pb-free part. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c03678-0-4/06(a)

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